- RS5: An Integrated Hardware and Software Ecosystem for RISC-V Embedded Systems
RS5 is a processor that implements the RISC-V 32-bit Integer Module (RV32I) alongside the Zicsr Extension and the RISC-V Privileged Architecture Machine Mode. It is written in the SystemVerilog Hardware Description Language (HDL). It also supports the M and C extensions, with some proprietary extensions, such as XASCON (crypto), XKYBER (PQC), and XOSM (a simple paging mechanism to support multitasking).
- RISC-V Processors Verification
Continuous Integration of RISC-V processors available at GitHub.
- RISC-V Matrix Processing Unit
This project focuses on developing a Matrix Processing Unit (MPU) to be attached or integrated into a RISC-V processor. This MPU aims to enhance computational efficiency and performance, pushing the boundaries of High-Performance Computing (HPC) and artificial intelligence workloads.
This is a partnership between Instituto ELDORADO, in collaboration with researchers from the State University of Campinas (UNICAMP), and the Barcelona Supercomputing Center (BSC). The initiative is part of the Priority Program for National Interest (PPI-Softex).
