RS5 is a processor that implements the RISC-V 32-bit Integer Module (RV32I) alongside the Zicsr Extension and the RISC-V Privileged Architecture Machine Mode. It is written in the SystemVerilog Hardware Description Language (HDL). It also supports the M and C extensions, with some proprietary extensions, such as XASCON (crypto), XKYBER (PQC), and XOSM (a simple paging mechanism to support multitasking).
Author: Fernando Gehm Moraes
Fernando Moraes received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1987 and 1990, respectively. In 1994, he received his Ph.D. from the Laboratoire d’Informatique, Robotique et Microélectronique de Montpellier (LIRMM), France. He is currently at PUCRS, where he has been an Associate Professor from 1996 to 2002 and a Full Professor since 2002. He joined the Université de Montpellier as an Invited Professor in 1998, 1999, 2000, and 2017 (1 to 3 months each period). He has authored and co-authored 58 peer-reviewed journal articles in VLSI design, including networks-on-chip (NoCs) and telecommunication circuits. He has also authored and co-authored over 270 conference papers on these topics. He has co-advised 4 MSCs, advised 32 MsC, advised 20 PhDs, and co-advised 3 PhD. His primary research interests include Microelectronics, FPGAs, reconfigurable architectures, security, NoCs, and MPSoCs (multiprocessor system on chip), RISC-V accelerators. SBC (Sociedade Brasileira de Computação), SBMICRO, and IEEE Senior Member.